Conventionally, downsizing and weight saving of electronics devices have been advancing, and with this advancement, there is demand for high-density package on substrates, and the downsizing, thinning and weight saving of semiconductor packages mounted on electronics devices are progressing. Conventionally, there have been packages called LOC (Lead On Chip) and QFP (Quad Flat Package), and packages such as μBGA (Ball Grid Array) and CSP (Chip Size Package) that are smaller and lighter than the packages such as LOC and QFP have been developed. Face-down type packages that are a flip chip, WL-CSP (Wafer Level Chip Size Package) etc. wherein a circuit surface of a semiconductor element is faced to the surface of a semiconductor interconnection substrate, have also been developed.
In the packages described above, sealed packages are obtained by transfer-molding a solid epoxy resin sealing material, but it is difficult to mold thin or large packages. When the content of inorganic fillers is increased, melt viscosity is generally increased at the time of transfer molding, to cause problems such as an increase of residual voids at the time of molding, of insufficient filling in a cavity, of wire flow and of stage shift, and deteriorations in the qualities of a molded product.
In recent years, some of the flip chips, WL-CSP etc. have protruded electrodes, and for protecting such protrusions and filling a gap between the protrusions, a sealing material has sometimes been used, but it has been difficult to fill thereof with a solid epoxy resin sealing material. Accordingly, a sealing film comprising an epoxy resin and an inorganic filler has been proposed (refer to, for example, Japanese Patent Application Laid-Open No. Hei 5-283456, Hei 5-190697, Hei 8-73621 and 2005-60584).